Suchen

Reducing Harmful dV/dt Transients from Switching Circuits

Autor / Redakteur: Zhongda Li * / Gerd Kucera

High voltage transient spikes generated during power conversion or gate-drive switching can be very harmful. In a motor drive application, the dV/dt transients may break the winding insulation, reducing motor life, and impacting system reliability.

Firmen zum Thema

Figure 1: Gate drive with an external Cgd for dV/dt control.
Figure 1: Gate drive with an external Cgd for dV/dt control.
(Credits: UnitedSiC)

In circuits that use silicon MOSFETs, IGBTs, and SiC MOSFETS, the usual way to reduce the transient response is to increase the value of the external gate resistor. Such devices typically have a high reverse transfer capacitance (Crss) or gate-drain Miller capacitance (Cgd). Increasing the gate resistance (Rg) is particularly effective at reducing dV/dt for fast switching applications. An example use case is a totem-pole PFC, where lower switching losses result from a high dV/dt. However, with slower applications, such as a motor, the resistance value required to achieve a dV/dt within an acceptable range of say 5 - 8 V/ns, would be in the kΩ range. A high Rg would lengthen the switch on and off delay considerably.

This article highlights three methods of bringing dV/dt from 45 V/ns down to 5 V/ns using an UnitedSiC FET without incurring excessive delay times. In this order, we investigate using an external gate-drain capacitor, RC snubbers on the device, and a JFET direct drive approach. A UnitedSiC 1,200 V SiC FET (UF3SC120009K4S) in a T0247-4L package with a Rdson of 9 milliΩ is used for each example. Switching is at 75 A / 800 V. Each scenario was first simulated using a SPICE model of the UnitedSiC SiC FET. Then circuit experiment measurements were made during turn-on and turn-off to verify the simulation results.

Bildergalerie
Bildergalerie mit 7 Bildern

Using an external Cgd capacitor

In this method, an external Cgd capacitor, Cgdext, is placed between the gate and drain of both the high- and low-side FETS of a half-bridge configuration (see Figure 1).

For the UnitedSiC part, the Cgdext value is calculated to be 68 pF, and, for simulation purposes, a series parasitic inductance (Lpar) of 20 nH in included. The parasitic inductance could be less in real situations using discretes and with the Cgd capacitors connected as close as possible to the FETs. If FET modules are used, the capacitor would need to be placed external to the module, this representing closer to 20 nH parasitic inductance. The results of the SPICE simulation and the experiment for the external Cgd capacitor are illustrated in Figure 2. Because Ids is relatively low during switching, estimated to be 0.54 A, the external capacitor can tolerate the 20 nH parasitic inductance. The dV/dt for this method was measured and calculated to be in the range 25 V/ns to 5 V/ns when using the 68 pF capacitor and an Rg in the range of 10 Ω to 33 Ω (see Figure 3).

The results indicated that this method of reducing dV/dt is appropriate for using with FET modules, placing Cgd on the PCB, and accepting a degree of parasitic inductance.

Using an RC snubber across each FET

Another way of controlling dV/dt is by connecting an RC snubber circuit across the drain and source of the high-side and low-side FETs (see Figure 4).

For this example, like the external gate-drain capacitor, a 20 nH parasitic inductance was added in series with the capacitor (Csnubber) and resistor (Rsnubber). When using discrete FETs, the RC components can be placed as closely as possible to the FETs, ideally directly to the leads, in which case the parasitic inductance would be minimal. The experimental snubber circuit used a 5.6 nF capacitor and a 0.5 Ω resistor. SPICE simulation and the results from the experiment indicated that the dV/dt could be reduced from 50 V/ns to 5 V/ns using this approach (see Figures 5 and 6).

Figure 5: Using an RC snubber across the drain-source of each FET. Measured traces are solid lines; SPICE simulation is dashed lines. The tests were conducted with a 5.6 nF capacitor and 0.5 Ω resistor in a 75 A, 800 V gate drive. Left waveforms turn off; right waveforms turn on.
Figure 5: Using an RC snubber across the drain-source of each FET. Measured traces are solid lines; SPICE simulation is dashed lines. The tests were conducted with a 5.6 nF capacitor and 0.5 Ω resistor in a 75 A, 800 V gate drive. Left waveforms turn off; right waveforms turn on.
(Credits: UnitedSiC)

Switching losses resulting from the addition of the snubber circuit were minimal with lower capacitance values, amounting to approximately 2 W with a 10 kHz switching frequency. The relatively high value of simulated parasitic inductance, 20 nH, indicated the RC snubber arrangement could be placed external to FET modules and reduce dV/dt by 90%.

The JFET direct-drive method to reduce dV/dt

Figure 7: 
In this circuit of a direct-drive JFET 
arrangement the Si MOS device is turned on once at start-up, and the JFET gate 
is switched between -15 V and 0 V.
Figure 7: 
In this circuit of a direct-drive JFET 
arrangement the Si MOS device is turned on once at start-up, and the JFET gate 
is switched between -15 V and 0 V.
(Credits: UnitedSiC)

The final method of reducing dV/dt is the use of a direct-drive JFET arrangement - see Figure 7. In this circuit, the Si MOS device is turned on once at start-up, and the JFET gate is switched between -15 V and 0 V. A PWM gate drive signal is required and an enable signal, but the normally off operation is maintained. The high-side JFET gate has -15 V applied to keep it off during switching transients. Again, measurements were conducted with an experimental setup and circuit simulation using a SPICE model. See the results in Figures 8 and 9. Since the SiC JFET has significant Crss(Cgd), a small Rg of 4.7 Ω is sufficient to slow down dV/dt to 5 V/ns.

Table 1: Summary of SPICE simulated performance for the three dV/dt reduction methods.
Table 1: Summary of SPICE simulated performance for the three dV/dt reduction methods.
(Source: UnitedSiC)

Conclusions: Table 1 highlights the summary SPICE simulated predictions of the three different methods of reducing the dV/dt in a 75 A/800 V circuit. Of the three, the JFET direct-drive approach produced the lowest energy loss. That said, the direct drive requires a -15 V drive signal, and an enable signal, adding to component count and circuit complexity.

The external Cgd capacitor and RC snubber methods showed slightly higher switching losses but do not require access to the JFET gate. Both of these methods can be easily achieved on a PCB when using discrete FETs.

Standard UnitedSiC FETS do not provide access to the gate of the JFET, but a new dual-gate product packaged in a TO247-4L package is in development. This approach is also suitable for use with modules that have a JFET gate pin added. In all cases, a 20 nH parasitic inductance was factored into the SPICE simulations, the results proving that a degree of inductance does not impact the reduction of dV/dt.

The RC snubber method highlighted that it could not control turn-on and turn-off dV/dt independently (see Table). However, separate Rgon and Rgoff resistors allow independent control for the Cgd and the direct drive JFET methods.

In this article, we have showcased three different approaches to significantly reducing dV/dt. The use of UnitedSiC FETs, with their low conduction losses and rugged characteristics in short-circuit conditions, makes these powerver devices an efficient and reliable choice for electrical motor drive developments.

* Dr. Zhongda Li is Senior Staff R&D Engineer, UnitedSiC.

Artikelfiles und Artikellinks

(ID:46899077)