An Alternative Cost-Effective Design Flow for Mixed-Signal ASICs

| Autor / Redakteur: Paul Double * / Holger Heller

There is a well-entrenched and long-held view in the industry that for ASIC design, in the digital, analogue or mixed-signal domain, the only tools that will to deliver a workable solution are those from the major EDA tool companies. The assumption is that low-cost IC design tools will not deliver the required functionality or have the necessary process design kit (PDK) support for the target foundries.

It can be argued that for a major chip company, designing leading-edge System-on-Chip processors or graphics controllers in 28nm process technology, to deliver world-class performance and ultra-low-power consumption, a multi-million dollar design tool flow might be the necessary choice. And certainly it’s the tools and integrated design flows targeting this segment of the market that grab all the headlines.

However, it’s also an extremely realistic and highly cost-effective proposition to use comparatively low-cost high-functionality tools in the design of, what can be described as, ‘mainstream’ ASICs. There are a host of EDA tools targeting the design of mixed-signal ASICs that offer close to the same levels of functionality and performance, but at a fraction of the traditional prices paid for leading-edge tools. Backed up by access to foundry PDKs, these tools offer an unrivalled mix of productivity and cost effectiveness.

EDA Solutions has proved this over many years working with the analogue and mixed-signal design tools from Tanner EDA. The tools deliver what designers need them to do, in conjunction with delivering excellent PDK services that enable designers to use these tools in their choice of process technology.


The market for mainstream analogue and mixed-signal ASICs in the mature process technologies is strong. The problems that were encountered at the 0.18- to 0.35-micron nodes were overcome 10 or 15 years ago. The tools and processes are mature, yields are high and the IP is tried and tested.

There are major analogue and mixed-signal foundries in Europe and elsewhere that do not offer the leading-edge process technologies, but are producing thousands of different ASICs, and in volumes of hundreds of thousands or even millions per year. And the companies that are making use of these fabs do not necessarily require leading-edge design tools that have been developed to overcome problems at 32 or 28nm and below.

These designs could include a few million gates in a 0.13- or 0.18-micron process running at a few hundred megahertz. These are not trite designs and are well within the capabilities of these tools, but have all the functionality required by designers at the mature technology nodes. Companies such as Tanner EDA, on the analogue and mixed-signal side, and Incentia Design Systems in the digital domain, have developed excellent tools for mainstream ASIC designs (although, in fact, Incentia tools have been used in customer tape-outs at the 32 and 28nm nodes.)

Increasing Costs

A major shift in the ASIC design industry over the past few years has increased concern about the Cost of Ownership (CoO) of EDA tools. Primarily, the larger tool vendor will issue time-based licenses for their tools. A company may invest in one or two years of time-based licenses, when a budget review is scheduled for future licenses. Price increases and functionality changes are always a surprise during the license renewal negotiations. Hence, there is a renewed interest in perpetual licenses in the ASIC design industry.

Paying for leading-edge tools from the larger EDA companies could mean paying $150,000 per year, and in three years time, depending on market conditions, it could be $200,000 or $250,000. Of course it could be less – but it is not predictable. After the initial cost of a perpetual license from Tanner or Incentia, for example, the only cost beyond this will be the annual maintenance fee, which provides access to user support, software upgrades, bug fixes, PDK support, and tools with new functionality.

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