Debugger

Multi-core is more than just multi-core

08.01.13 | Autor / Redakteur: Heiko Riessland * / Holger Heller

PLS Universal Access Device 3+ (UAD3+): with debug and Aurora trace pods on an Aurix target
Bildergalerie: 5 Bilder
PLS Universal Access Device 3+ (UAD3+): with debug and Aurora trace pods on an Aurix target (PLS)

When using MCU multi-core architectures for "deeply embedded" applications, different rules apply for symmetric multiprocessing on identical cores with support of an encapsulating OS. This poses an entirely new set of challenges for chip suppliers, tool manufacturers and users.

For many years now, multi-core devices have become popular in the area of traditional microprocessors. In 2003, with its MPCore, ARM already presented a multi-core concept. At first, however, this was only a matter of integrating an ARM core, a digital signal processor (DSP) and maybe additional functional units.

Among other things, the concept was used in Qualcomm’s Snapdragon processors that were available at the end of 2008. In 2006, with the Core 2, Intel presented the first multi-core architecture for PC applications.

This was followed in 2008 with the first ARM Cortex MPCore architecture. In 2011, it was used for the first time in the Tegra 2 System-on-Chip (SoC), which is equipped with two Cortex-A9 cores and an additional six special processors for video, audio, etc. The Tegra 2 was the heart of the LG P990 Optimus Speed Smartphone.

With conventional microprocessors, we are dealing almost exclusively with symmetric multiprocessing (SMP) on identical cores. In this case, as a rule, an operating system encapsulates the sharing of the program execution to the individual cores for the application developer.

However, with multi-core microcontrollers for "deeply embedded" automotive or industrial applications, semiconductor manufacturers, tool suppliers and the users are confronted with a completely new initial situation.

Besides considerable differences in performance and target applications, multi-core devices from Freescale’s Qorivva family, Infineon’s Aurix family, some of Freescale’s Vybrid family or NXP’s LPC4300 devices, all have one thing in common: Different cores can be combined with each other for a System-on-Chip (SoC). With Aurix (AUtomotive Realtime Integrated NeXt Generation Architecture) and Qorivva devices, which are ideally suited for automotive applications with high performance requirements; these are different TriCore and e200 cores respectively.

With multi-core devices of Freescale’s Vybrid family, it’s a combination of an ARM Cortex-A5 core with an ARM Cortex-M4 core and with NXP’s LPC4300 family it’s a combination of an ARM Cortex-M4 with an ARM Cortex-M0. Vybrid and LPC4300 microcontrollers are mainly used in industrial automation applications or in less power-hungry automotive applications.

Concurrency challenges multi-core designs

In most cases, the motivation to use multi-core architectures at all is the desire for higher performance and/or the reduction of electrical power consumption. With single core architecture, the supposedly obvious way to arbitrarily increase performance by increasing the clock frequency is now running up against its physical limits.

Not only the unavoidable increase in power consumption and resulting heat generated on the chip associated with higher clock frequencies are a cause of concern for designers, but also the controllability itself of the high clock frequencies. In this regard, the use of multiple cores is a tempting alternative, because a boost in performance can be achieved as a result without increasing the system clock, and the increase in electrical power consumption is significantly lower than through increasing the clock frequency.

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